Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform

This paper describes a motion estimation co-processor architecture that explicitly separates the implementation stages consisting of data access to the search window and the evaluation of the matching criterion from the implementation of the search strategy. The architecture is modular and can be re-configured according to the different MPEG video coding profiles and level parameters. Although the architectural solutions described here can be in principle applied to any SoC implementation technologies, the solution presented here is expressly conceived and validated on FPGA co-processing architectures supporting mixed SW/HW implementations of video encoders such as generic PC platforms with a standard PCMCIA FPGA cards. The module has been developed in the framework of the MPEG reference hardware description activity.