Overcoming the limitations of Al metal line patterning technology without damascene process

Etch patterning process using Al wiring is technical challenging in sub-280 nm pitch devices especially when Cu damascene process is not available in 8 inch wafer semiconductor fabrication facilities. However, some of the CMOS image sensors (CIS) at our company are designed to meet back end of layers (BEOL) minimum design rule (DR) of 200 nm pitch (Bar/Space 100/100nm) without damascene process. In addition to meeting the pitch requirement, the vertical profile of the metal 1 should be suitable for the characteristics of its optical sensor. If we cannot perform the metal 1 layer module process and patterning implementation, the optical attribute called Brightness(Y) Signal to Noise Ratio (YSNR) will decline, which is the most important part of the product. Moreover, electrical attributes and yield requirements cannot be achieved. Fig. 1. and 2. show the top and vertical view of the present CIS metal 1 profiles. In this paper, we optimized etch module process to realize fine metal pattern of CIS products which are based on Al wiring in 200nm pitch without using damascene process.