Analysis of field variation on threshold voltage and drain current of NMOS using TCAD

Threshold voltage of NMOS plays a pivotal role in deciding the transistor operating region and it should be large enough to provide minimum offset current. Drain current is also a key factor which decides the power dissipation by the transistor. Threshold voltage and drain current depends upon several parameters. In this paper, 0.13μm channel length NMOS has been taken and the effect of field variation has been studied on drain current and threshold voltage. TCAD version 1.7.4-9(#2e12095) is used for designing and simulation of NMOS. The gate thickness is varied from 4nm to 10nm. SiO₂ is used as an oxide layer. The drain voltage is kept constant at 0.3V and gate to source voltage is varied from 0 to 2V. Source and body terminal are kept at zero potential. The transfer characteristics has been plotted and also the inversion layer variation is being plotted with different field strengths.