Circuit topology considerations for energy efficient design of data-driven systems

The concept of energy efficiency for data driven applications is proposed in this paper as a relationship between energy dissipation and throughput delay, on equal amounts of data processed, defined as energy per bit and bit rate. We investigated several degrees of parallelism in circuits with the same functionality in terms of delay and energy consumption. We modeled two scenarios in data driven systems and identified the optimal points for both, in our proposed design space.