Title :
Decoding algorithm for the high-dimensional discrete torus knot code
Author :
Hata, Masayasu ; Yamaguchi, Eisaku ; Takumi, Ichi ; Hamasuna, Yuuichi ; Miyoshino, Kenji
Author_Institution :
Aichi Prefectural Univ., Japan
Abstract :
A majority logic decoding is suitable for ASIC design of the proposed code. A four-dimensional size-five code of 625-bit length was implemented on a VLSI and attained an operation speed up to 50 Mbps and 32-bit burst correction
Keywords :
VLSI; application specific integrated circuits; decoding; majority logic; 32 bit; 50 Mbit/s; ASIC design; VLSI; decoding algorithm; four-dimensional size-five code; high-dimensional discrete torus knot code; majority logic decoding; operation speed; Application specific integrated circuits; Error analysis; Error correction; Error correction codes; Iterative decoding; Logic design; Parity check codes; Robustness; Solids; Very large scale integration;
Conference_Titel :
Information Theory, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Sorrento
Print_ISBN :
0-7803-5857-0
DOI :
10.1109/ISIT.2000.866349
