DocumentCode
2385458
Title
A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET
Author
Sakui, Koji ; Endoh, Tetsuo
Author_Institution
Center for Interdiscipl. Res., Tohoku Univ., Sendai, Japan
fYear
2010
fDate
22-25 March 2010
Firstpage
220
Lastpage
224
Abstract
The concept of the measurement technique is to separate the paths by at least two directions; one is the current path, where the drain current flows, and the other is the non-current path, where the voltage is measured with the connection to the high-Z gate of the monitor circuit. The proposed measurement technique has been validated by HSPICE simulation.
Keywords
MOSFET; measurement systems; HSPICE simulation; asymmetric bottom-pillar resistance; current path; extraction technique; measurement technique; noncurrent path; vertical MOSFET; Electric resistance; Geometry; MOSFET circuits; Microelectronics; Research and development; Resistors; Signal processing; Stochastic processes; Stochastic systems; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location
Hiroshima
Print_ISBN
978-1-4244-6912-3
Electronic_ISBN
978-1-4244-6914-7
Type
conf
DOI
10.1109/ICMTS.2010.5466812
Filename
5466812
Link To Document