Test structures to quantify contact placement-impacted drain current variations

The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results and provide a means to extract mean contact resistance from our test structures. We observe that impact due to contact resistance can be up to 10% for 45 nm, while it could have been of less importance (less than 4%) for 65 nm technology. Such test structures and methodology help us provide intrinsic device models in 45 nm without inaccuracies or resistive double counting that may be introduced due to placement-impacted contact resistance variations.