Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

This paper summarizes a comprehensive study on the effect of asymmetrical metal coverage on matching performance for a 45 nm copper damascene based CMOS process. We demonstrate that random mismatch fluctuations are not affected by metal layout asymmetries and we provide valuable new insights about the magnitude of systematic mismatches that can be expected due to asymmetrical layouts and CMP tiling. For the first time we also present results on the impact of temperature increases on both systematic as well as random drain current mismatches.