An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions

An efficient exclusion of intra-DUT parasitic capacitances has been enabled by a combination of capacitance measurement and 3D capacitance simulation on structures with varying number of contacts per side for a MOSFET structure. Accounted for is the capacitance shift due to the presence of contact plugs, the physical shapes of which are not necessarily the same as their geometrical representations in design space.