Title :
Test structures for characterization of through silicon vias
Author :
Stucchi, M. ; Perry, D. ; Katti, G. ; Dehaene, W.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
As silicon technology reaches extreme sub-um dimensions, the industry has reached for ¿more than Moore¿ solutions to enable advancements in integration, lower system cost, and improve packaging footprints. Probably the best known of the more-than-Moore solutions is 3D chip stacking using through silicon vias (TSVs). This technology requires accurate characterization of the TSV, the thinned silicon, and the stacked die. Our paper deals with TSV characterization by means of specially designed test structures.
Keywords :
integrated circuit testing; three-dimensional integrated circuits; 3D chip stacking; more-than-Moore solutions; packaging footprints; silicon technology; stacked die; test structures; thinned silicon; through silicon vias; Silicon; Testing; 3D stack; RO (Ring Oscillator); SPICE simulations; TSV (Through Silicon Via); TSV resistance; capacitance; electrical measurements; leakage; yield;
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location :
Hiroshima
Print_ISBN :
978-1-4244-6912-3
Electronic_ISBN :
978-1-4244-6914-7
DOI :
10.1109/ICMTS.2010.5466841
