DocumentCode
2385996
Title
An embedded process monitor test chip architecture
Author
Idgunji, Sachin ; Chandra, Vikas ; Pietrzyk, Cezary ; Iqbal, Imran ; Aitken, Rob ; Yeric, Greg
Author_Institution
R&D, ARM, San Jose, CA, USA
fYear
2010
fDate
22-25 March 2010
Firstpage
122
Lastpage
127
Abstract
We present a test chip architecture which embeds a thorough set of process characterization ring oscillators into a synthesized digital circuit, such as a processor core. We discuss the motivation, implementation, and results from sub-40nm technology silicon.
Keywords
circuit testing; microprocessor chips; oscillators; embedded process monitor test chip architecture; process characterization ring oscillators; processor core; size 40 nm; synthesized digital circuit; Circuit testing; Data analysis; Microprocessors; Monitoring; Production; Ring oscillators; Semiconductor device testing; Silicon; Standards organizations; USA Councils; Design for Testability; Semiconductor Device Measurements; Semiconductor Device Testing; Yield Optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2010 IEEE International Conference on
Conference_Location
Hiroshima
Print_ISBN
978-1-4244-6912-3
Electronic_ISBN
978-1-4244-6914-7
Type
conf
DOI
10.1109/ICMTS.2010.5466842
Filename
5466842
Link To Document