Silicon characterization of standby leakage reduction techniques in a 0.13 μm Low Power Partially-Depleted Silicon-On-Insulator Technology

This paper presents silicon characterization results of various power gating techniques in a 0.13mum low power PD-SOI technology. A standby leakage current comparison is performed for floating body, body contacted and DTMOS transistors. It is shown that sleep transistors composed of PMOS in DTMOS configuration with an increased channel length are the best devices to reduce leakage power consumption in standby mode. Furthermore, on one hand, SOI helps reducing dynamic power consumption by more than 40% compared to bulk, and on the other hand, by implementing leakage reduction techniques, the standby leakage power is lowered by one decade