DocumentCode
2386147
Title
Leakage Reduction at Architectural Level
Author
Piguet, Christian ; Schuster, Christian ; Nagel, Jean-Luc
Author_Institution
CSEM & EPFL
fYear
0
fDate
0-0 0
Firstpage
1
Lastpage
4
Abstract
In very deep submicron technologies, the leakage power consumption becomes an important contribution to the total power consumption. This paper focuses on architecture comparison and aims at selecting the one with the minimum total power consumption by simultaneously optimizing static and dynamic power dissipations. As an example, the choice of one multiplier over eleven 16-bit multiplier architectures has been performed regarding the lowest total power
Keywords
integrated circuit design; leakage currents; logic design; low-power electronics; multiplying circuits; 16 bit; dynamic power dissipation; leakage reduction; multiplier architectures; static power dissipation; very deep submicron technologies; Capacitance; Employee welfare; Energy consumption; Frequency; Leakage current; Power dissipation; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
Conference_Location
Padova
Print_ISBN
1-4244-0097-X
Type
conf
DOI
10.1109/ICICDT.2006.220780
Filename
1669367
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