DocumentCode
2386207
Title
Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab
Author
Ho, C.M. ; Chen, T.C. ; Hseih, P. ; Chu, C. ; Houn, E. ; Su, K.J. ; Wang, P.M. ; Yew, W.C. ; Sun, S.W.
Author_Institution
United Microelectron. Corp., Hsin-Chu, Taiwan
fYear
2000
fDate
2000
Firstpage
63
Lastpage
66
Abstract
A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output increase of over 20%. In the mean time, the fab WIP level was reduced by more than 20% without any compromise in line-yield or customer delivery.
Keywords
integrated circuit manufacture; production control; 6 inch; case study; customer delivery; cycle-time reduction; fab WIP level; fully loaded foundry wafer fab; line-yield; output enhancement; production control; Capacity planning; EPROM; Foundries; Lithography; Microelectronics; Monitoring; Production control; Sun; Technological innovation; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
ISSN
1523-553X
Print_ISBN
0-7803-7392-8
Type
conf
DOI
10.1109/ISSM.2000.993617
Filename
993617
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