A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations

Author

De Vos, J. ; Haspeslagh, Luc ; Demand, Marc ; Devriendt, Katia ; Wellekens, Dirk ; Beckx, Stephan ; Houdt, J.V.

Author_Institution

IMEC, Leuven

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

4

Abstract

In this paper a scalable stacked gate technology with self-aligned floating gate (FG) is presented. It can be used for both NOR and NAND flash architectures. By introducing high-k materials for the interpoly dielectric (IPD) a planar structure can be used, which allows a much denser structure. It is also shown that the planar structure of the memory cell facilitates the introduction of metal gates. The successful integration of a 110nm stacked gate transistor with high-k IPD and TiN metal gate is illustrated

Keywords

NAND circuits; NOR circuits; dielectric materials; flash memories; titanium compounds; 110 nm; 45 nm; NAND flash technology; NOR flash technology; TiN; high-k metal gates; interpoly dielectric; memory cell; scalable stacked gate technology; self aligned floating gate; stacked gate transistor; Character generation; Controllability; Etching; Filling; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Nonvolatile memory; Slurries; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on

Conference_Location

Padova

Print_ISBN

1-4244-0097-X

Type

conf

DOI

10.1109/ICICDT.2006.220783

Filename

1669370