Design of optimized reversible binary adder/subtractor and BCD adder

Reversible logic has gained the interest of many researchers due to its applicability in emerging low power technologies such as Quantum computing, QCA, optical computing etc., Adders/Subtractors are basic design components of any processor. Optimized design of these adders results in efficient processors. In this work we propose optimized Binary adders/subtractors and BCD adders. The adders/subtractors designed in this work are optimized for Quantum cost and Delay. We also propose a generic design of n-bit adders and subtractors. In this work, we explore the use of Negative control lines for detecting overflow logic of BCD adder which considerably reduces Quantum cost, delay and gate count which result in high speed BCD adder with optimized area which give way to lot of scope in the field of reversible computing in near future.