Title :
A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology
Author :
Sankaran, S. ; Arai, S. ; Augur, R. ; Beck, M. ; Biery, G. ; Bolom, T. ; Bonilla, G. ; Bravo, O. ; Chanda, K. ; Chae, M. ; Chen, F. ; Clevenger, L. ; Cohen, S. ; Cowley, A. ; Davis, P. ; Demarest, J. ; Doyle, J. ; Dimitrakopoulos, C. ; Economikos, L. ; Ed
Author_Institution :
IBM Syst. & Technol. Group, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
Abstract :
A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria
Keywords :
CMOS integrated circuits; ball grid arrays; copper; flip-chip devices; integrated circuit interconnections; integrated circuit metallisation; plasma CVD coatings; silicon compounds; 45 nm; BEOL technology; CMOS; Cu; SiCOH; back end of line; circuit performance estimates; dual damascene scheme; homogeneous ILD; nonpoisoning damascene; organic flip-chip FCPBGA packages; ultra low-k PECVD; ultra low-k chip-package; wiring levels; CMOS technology; Circuit optimization; Costs; Etching; Integrated circuit reliability; Mechanical factors; Packaging; System performance; Wire; Wiring;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0439-8
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346782
