• DocumentCode
    2386368
  • Title

    Evaluation of the robustness of dual rail logic against DPA

  • Author

    Razafindraibe, A. ; Maurine, P. ; Robert, M.

  • Author_Institution
    LIRMM, Montpellier
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual rail logic is carried out. The result of this investigation is the formal identification of the design range in which dual rail logic can be considered as robust
  • Keywords
    CMOS logic circuits; logic design; CMOS cell; differential power analysis; dual rail logic; formal identification; switching current; CMOS logic circuits; CMOS process; Current measurement; Energy consumption; Information retrieval; Logic design; Propagation delay; Rails; Robustness; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
  • Conference_Location
    Padova
  • Print_ISBN
    1-4244-0097-X
  • Type

    conf

  • DOI
    10.1109/ICICDT.2006.220792
  • Filename
    1669379
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2386368