Efficient implementation of 8-bit vedic multipliers for image processing application

Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.