DocumentCode
2386752
Title
A Novel FDSOI MOSFET with Block Oxide Enclosed Body
Author
Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Huang, Kuo-Dong ; Lee, Tai-Yi ; Lin, Kao-Cheng
Author_Institution
Dept. of Electr. Eng., National Sun Yat-Sen Univ., Kaohsiung
fYear
0
fDate
0-0 0
Firstpage
1
Lastpage
4
Abstract
In this paper, we propose a novel fully depleted silicon-on-insulator MOSFET with block oxide enclosed body (bFDSOI). To differ with the conventional FDSOI MOSFET, the proposed SOI structure shows enhanced performance by exploiting sidewall spacer process. For this new bFDSOI device, the electric field between the body and the source/drain (S/D) region is restrained by the block oxide resulting in that the ultra-short-channel effects (USCEs) are suppressed. Thus, the simulation results of bFDSOI exhibit reduced drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), good roll-off characteristics and high drain output resistance for 40 nm thick enough body. In order to eliminate the floating-body problem, the bFDSOI device must not be operated under the partially depleted (PD) regime. Although this is the limit of device design, as the gate length is scaled down, the requirement of the ultra-thin body (UTB) structure is not needed to maintain its ultra-short-channel characteristics control over the channel due to the block oxide serves as isolation between the body and the S/D region. Moreover, owing to that the sufficient thick body is used; the bFDSOI device results in good amelioration of self-heating effects (SHEs), which is very important in a nano-scale SOI MOSFET design
Keywords
MOSFET; semiconductor device models; silicon-on-insulator; 40 nm; block oxide enclosed body; drain-induced barrier lowering; floating-body problem; fully depleted silicon-on-insulator; nanoscale SOI MOSFET design; self-heating effects; sidewall spacer process; subthreshold swing; ultra-short-channel effects; CMOS technology; Electric resistance; Fabrication; Immune system; Insulation; Lithography; MOSFET circuits; Silicon on insulator technology; Substrates; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
Conference_Location
Padova
Print_ISBN
1-4244-0097-X
Type
conf
DOI
10.1109/ICICDT.2006.220813
Filename
1669400
Link To Document