Title :
Yield model with redundancy based on critical area calculations
Author :
Mitsutake, K. ; Ushiku, Y.
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
Abstract :
To optimize the redundancy design, the yield model with redundancy is proposed. In this model the accurate number of redundancies to repair one fault is taken into consideration. The calculated yield with redundancy by using this model and the real one are in good agreement. As a result of the application for several redundancy designs, a guide to obtain higher yield is presented
Keywords :
integrated circuit design; integrated circuit modelling; integrated circuit yield; redundancy; critical area calculations; defect repair; fault repair; redundancy design; yield model; Design engineering; Design optimization; Manufacturing processes; Microscopy; Probability; Redundancy; Semiconductor device manufacture; Semiconductor device modeling; Virtual manufacturing;
Conference_Titel :
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
0-7803-7392-8
DOI :
10.1109/ISSM.2000.993645
