DocumentCode :
2386859
Title :
Statistical Minimization of Total Power under Timing Yield Constraints
Author :
Orshansky, Michael
Author_Institution :
Texas Univ., Austin, TX
fYear :
0
fDate :
0-0 0
Firstpage :
1
Lastpage :
4
Abstract :
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31% and total power by 17% without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30times faster than other known statistical power minimization algorithms
Keywords :
circuit analysis computing; integrated circuit design; leakage currents; low-power electronics; minimisation; statistical analysis; timing; conic problem; deterministic optimization; interior-point optimization; parametric yield; power minimization; power reduction; power yield; simultaneous sizing; statistical minimization; timing yield constraints; voltage assignment; Circuits; Constraint optimization; Delay; Design optimization; Leakage current; Performance loss; Robustness; Runtime; Threshold voltage; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on
Conference_Location :
Padova
Print_ISBN :
1-4244-0097-X
Type :
conf
DOI :
10.1109/ICICDT.2006.220818
Filename :
1669405
Link To Document :
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