DocumentCode
2387415
Title
Dynamic load balancing among multiple fabrication lines
Author
Toba, Hiroyasu ; Yonekura, Masaki
Author_Institution
Inf. Syst. Div., NEC Corp., Kanagawa, Japan
fYear
2000
fDate
2000
Firstpage
343
Lastpage
346
Abstract
We propose a load balancing method which balances all processing operations of products among multiple semiconductor wafer fabrication lines by using predictive scheduling results. From our simulation experiment we confirmed that the proposed method achieves a moderate load balancing feature among multiple fabrication lines each of which can independently fabricate wafers and has different wafer processing capacity. The load balancing feature effectively works to reduce waiting time at each process step and lead time of all products in multiple fabrication lines.
Keywords
integrated circuit economics; integrated circuit layout; integrated circuit manufacture; integrated circuit modelling; process control; production control; semiconductor process modelling; wafer-scale integration; dynamic load balancing; lead time; multiple fabrication lines; predictive scheduling; processing operations; semiconductor wafer fabrication lines; waiting time; Dispatching; Electron devices; Fabrication; Job shop scheduling; Lead time reduction; Load management; Manufacturing processes; National electric code; Production; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on
ISSN
1523-553X
Print_ISBN
0-7803-7392-8
Type
conf
DOI
10.1109/ISSM.2000.993683
Filename
993683
Link To Document