Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

Author

Singh, N. ; Lim, F.Y. ; Fang, W.W. ; Rustagi, S.C. ; Bera, L.K. ; Agarwal, A. ; Tung, C.H. ; Hoe, K.M. ; Omampuliyur, S.R. ; Tripathi, D. ; Adeyeye, A.O. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.L.

Author_Institution

Inst. of Microelectron., Singapore

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of I_d-V_g oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well

Keywords

MOSFET; crystal orientation; nanowires; CMOS devices; carrier confinement; channel orientation; crystal orientation; gate control; gate-all-around; silicon-nanowire MOS transistors; Carrier confinement; Dry etching; Fabrication; Lithography; MOSFET circuits; Nanoscale devices; Silicon; Temperature sensors; Threshold voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0438-X

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346840

Filename

4154259