Title :
Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
Author :
Shino, Tomoaki ; Kusunoki, Naoki ; Higashi, Tomoki ; Ohsawa, Takashi ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Ikumi, Nobuyuki ; Matsuoka, Fumiyoshi ; Kajitani, Yasuyuki ; Fukuda, Ryo ; Watanabe, Yoji ; Minami, Yoshihiro ; Sakamoto, Atsushi ; Nishimura, Jun
Author_Institution :
Center for Semicond. R&D, Toshiba Corp., Yokohama
Abstract :
Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
Keywords :
DRAM chips; nanoelectronics; 16 MByte; 32 nm; 43 nm; DRAM chips; data retention time constant; floating body RAM; signal margin; silicon-on-insulator; threshold voltage difference; Circuits; Data mining; Fabrication; Information systems; Large scale integration; Microelectronics; Random access memory; Read-write memory; Scalability; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0439-8
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346846
