Author :
Tran, T. ; Weis, R. ; Sieck, A. ; Hecht, T. ; Aichmayr, G. ; Goldbach, M. ; Wang, P.-F. ; Thies, A. ; Wedler, G. ; Nuetzel, J. ; Wu, D. ; Eckl, C. ; Duschl, R. ; Kuo, T.-M. ; Chiang, Y.-T. ; Mueller, W.
Abstract :
The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
Keywords :
DRAM chips; MIS devices; capacitors; nanoelectronics; 512 MByte; 58 nm; inter-level dielectric; metal-in-collar; metal-insulator-silicon devices; trench DRAM technology; trench capacitor; Capacitance; Capacitors; Dielectric substrates; Doping profiles; Etching; Metal-insulator structures; Random access memory; Region 3; Space charge; Tunneling;
