Author :
Kawano, M. ; Uchiyama, S. ; Egawa, Y. ; Takahashi, N. ; Kurita, Y. ; Soejima, K. ; Komuro, M. ; Matsui, S. ; Shibata, K. ; Yamada, J. ; Ishino, M. ; Ikeda, H. ; Saeki, Y. ; Kato, O. ; Kikuchi, H. ; Mitsuhashi, T.
Abstract :
A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability
Keywords :
DRAM chips; fine-pitch technology; integrated circuit layout; silicon; 3 Gbit/s; 3D packaging; 4 GByte; SMAFTI technology; Si; data transfer; feedthrough interposer; stacked DRAM chips; through-silicon vias; Design optimization; Filling; Packaging; Random access memory; Silicon; Through-silicon vias; Transfer functions; Wafer bonding; Wafer scale integration; Wiring;
