FPGA implementation of enhanced key expansion algorithm for Advanced Encryption Standard

Cryptography is a technique related to aspects of information security such as data confidentiality, data integrity and entity authentication. In data and telecommunication systems, Security is the most important part for an effective communication, where to increase the security as well as complexity, more randomization in secret keys is necessary to enhance the cryptography algorithms. In traditional AES, Even though the round keys have high security, Power analysis attack and Saturation attack are effective to the key expansion algorithm of AES due to the deducible key rounds and it leads to security problems. As a result, a new algorithm for generation of round keys is developed for AES. On hardware platform, these algorithms are realizing with enormous memory spaces and large execution time. An alternative hardware platform scenario is provided by Field programmable gate arrays (FPGAs) due to its reconfiguration nature, marketing speed and low price. Accordingly, a hardware implementation of the AES-128 encryption and decryption algorithm with the new algorithm of round key expansion is proposed to improve the security against such attacks. This structure will experimentally simulate using Xilinx software with Verilog HDL and hardware implementation on FPGA.