Switching State Vector Selection Strategies for Paralleled Multilevel Current-Fed Inverter Under Unequal DC-Link Currents Condition

A paralleled multilevel inverter topology consists of n three-phase three-level current-fed inverters (CFIs) connected in parallel on ac side. AC currents with (2n+1) levels can be generated utilizing redundant switching states when all three-level inverters have equal dc-link currents. However, the multilevel space vector diagram gets modified, redundancy in the switching states is lost and the multilevel current pattern changes when the dc-link current of all inverters is not the same. This introduces low-frequency harmonics in output current, thereby deteriorating total harmonic distortion (THD). The presence of low-frequency components in the output current could be avoided by selecting suitable switching state vectors and ensuring proper time sharing among these vectors. Two methods to select such switching state vectors are proposed in this paper. In the first method, a reference current space vector is realized using the nearest switching state vectors. However, this method results in low-frequency pulsation in dc-link voltage of each inverter. In the second method, the switching state vectors are chosen to eliminate this low-frequency pulsation. Effectiveness of these methods is experimentally validated for a five-level CFI. Further, performance of these methods is compared based on efficiency, THD, and dc-link voltage ripple for various inequality ratios in dc-link currents.