Author :
Kirsch, P.D. ; Quevedo-Lopez, M.A. ; Krishnan, S.A. ; Krug, C. ; AlShareef, H. ; Park, C.S. ; Harris, R. ; Moumen, N. ; Neugroschel, A. ; Bersuker, G. ; Lee, B.H. ; Wang, J.G. ; Pant, G. ; Gnade, B.E ; Kim, M.J. ; Wallace, R.M. ; Jur, J.S. ; Lichtenwalner
Abstract :
We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (VT =0.33V), low equivalent oxide thickness (EOT=0.91nm) (Tinv =1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070degC, 3) interlayer SiO2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI tradeoff, while matching the VT of a SiO2/n-PolySi control
Keywords :
MOSFET; carrier mobility; hafnium compounds; high-temperature electronics; lanthanum compounds; silicon compounds; stability; HfLaSiON; SiO2; band edge n-MOSFET; carrier mobility; high temperature stability; high-k/metal gate stacks; low equivalent oxide thickness; low threshold voltage; plasma nitridation; post nitridation anneal; reduced bias temperature instability; Annealing; Crystallization; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Plasma temperature; Stability; Threshold voltage; Tuning;
