Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices

Author

Singanamalla, R. ; Ravit, C. ; Vellianitis, G. ; Petry, J. ; Paraschiv, V. ; van Zijl, J.P. ; Brus, S. ; Verheijen, M. ; Weemaes, R.G.R. ; Kaiser, M. ; van Berkum, J.G.M. ; Bancken, P. ; Vos, R. ; Yu, H. ; De Meyer, K. ; Kubicek, S. ; Biesemans, S. ; Hook

Author_Institution

KU Leuven

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

We report band-edge pFET threshold voltage (V_t ~ 0.28 V) for MoO_xN_y on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs V_t of 0.45 V using a MoO _x/SiON gate stack, meeting the requirement for 45nm high-V _t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoO_x/SiON and MoO_x/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO_xN_y gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices

Keywords

CMOS integrated circuits; MOSFET; dielectric materials; electrodes; hafnium compounds; molybdenum compounds; silicon compounds; 0.45 V; 45 nm; CMOS technology; HfSiON; MoON; band-edge pFET; dielectric integrity; gate dielectric; metal gate electrodes; metal-inserted poly-stack process flow; pMOSFET devices; threshold voltage; Atherosclerosis; CMOS technology; Dielectrics; Electrodes; Fabrication; Implants; MOSFET circuits; Plasma applications; Plasma properties; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346864

Filename

4154283