Advanced SOI technologies: advantages and drawbacks

Author

Faynot, O. ; Poiroux, T. ; Andrieu, F. ; Jahan, C. ; Barraud, S. ; Ernst, T. ; Brévard, L. ; Deleonibus, S.

Author_Institution

LETI, CEA, Grenoble

fYear

0

fDate

0-0 0

Firstpage

200

Lastpage

203

Abstract

ITRS roadmap requires a reduction of the device dimensions, with an enhancement of its intrinsic performance: both electrostatic behavior improvement and mobility enhancement are required at the same time. The use of SOI substrates can provide a solution for the electrostatic issue. Indeed, in addition to the classical single gate SOI transistors, novel multiple gate devices are fabricated: the increase of the number of gate is a guaranty of performance enhancement. Regarding mobility aspects, several unique solutions are under development on SOI in order to boost the transistor drive current. The purpose of this paper is to make a review of all the different transistor architectures available on SOI, as well as all the solutions provided for mobility enhancement

Keywords

silicon-on-insulator; transistors; SOI substrates; Si; device dimensions; electrostatic behavior; mobility enhancement; multiple gate devices; single gate SOI transistors; transistor drive current; CMOS technology; Circuit optimization; Doping; Electronic mail; Electrostatics; Epitaxial growth; FinFETs; Immune system; Silicon on insulator technology; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2006. IWJT '06. International Workshop on

Conference_Location

Shanghai

Print_ISBN

1-4244-0047-3

Type

conf

DOI

10.1109/IWJT.2006.220892

Filename

1669479