Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence

Carrier velocity in the MOSFET channel at the top of the barrier near the source (virtual source) is the main driving force for improved transistor performance with scaling. This paper uses an analytical model that relates MOSFET intrinsic delay to key technology parameters and presents a methodology for extracting those parameters from literature benchmark papers. A historical trend of channel velocity including the most recent results of strain engineering is presented and is extrapolated to what is required in order for the performance scaling trend to continue. Key findings and their theoretical explanations include: (1) the traditional CV/I delay metric is overly optimistic, (2) the ITRS´05 prediction approach is also overly optimistic because it relies on incorrect V_T and unrealistic parasitics, (3) carrier mobility is much more closely correlated with velocity than previously believed, and (4) uniaxially strained Si is not able to meet the requirements for 10 nm gate length