Integration of ultra-shallow junctions in sub-0.1 /spl mu/m CMOS transistors : what kind of process for a "safe" advanced technology?

Facing the difficulty to reach the International Technology Roadmap (ITRS) in junction technology with the conventional approach numerous alternative doping processes have been recently developed to fabricate very-well activated and shallow p/sup +//n junctions. Taking into account that such processes present many challenges to solve for their integration, we choose to re-examine, in this paper, the ITRS targets. We show that the series resistance requirements can be achieved with the usual processes (ion implantation and rapid thermal annealing) for the 100 nm node. Furthermore, we demonstrate that the ITRS process window can be enlarged toward shallower junctions with relaxed sheet resistance. For sub-100 nm technologies, we identify the integration process issues for the usual doping processes. Tied with the anomalous diffusion of the implanted boron profile tail during the spacer deposition in one hand, with the coupled diffusion due to the source/drain implants in the other hand, we propose the Plasma Doping (PLAD) technique as a solution to resolve these issues. The viability of our strategy is demonstrated by fabricating very-well controlled 60 nm pMOSFETs with PLAD in a standard architecture.