DocumentCode :
2388643
Title :
Implementation of a dual-phase lock-in amplifier on a TMS320C5515 digital signal processor
Author :
Hofmann, M. ; Bierl, R. ; Rueck, T.
Author_Institution :
Sensorik Applikationszentrum (SappZ), Regensburg Univ. of Appl. Sci., Regensburg, Germany
fYear :
2012
fDate :
13-14 Sept. 2012
Firstpage :
20
Lastpage :
24
Abstract :
A digital dual-phase lock-in amplifier that is capable to run on a low-cost, low-power platform comprising a 16-bit fixed-point digital signal processor was developed. This is achieved by a set of optimised digital filters including an exponential averager to adjust the time constant of the overall filter. The reference frequency is generated using a direct digital synthesis source utilising angle decomposition with a resolution of 1 Hz. The digital lock-in algorithm is described and the performance of the algorithm is analysed. The experimental results show that the developed lock-in amplifier achieves similar performance to a commercially available lock-in amplifier.
Keywords :
amplifiers; digital filters; digital signal processing chips; direct digital synthesis; low-power electronics; TMS320C5515 digital signal processor; angle decomposition; digital lock-in algorithm; direct digital synthesis source; dual-phase lock-in amplifier; exponential averager; fixed-point digital signal processor; frequency 1 Hz; low-cost low-power platform; optimised digital filters; reference frequency; word length 16 bit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Education and Research Conference (EDERC), 2012 5th European DSP
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4673-4595-8
Electronic_ISBN :
978-1-4673-4595-8
Type :
conf
DOI :
10.1109/EDERC.2012.6532217
Filename :
6532217
Link To Document :
بازگشت