Author :
Ball, M. ; Rosal, J. ; McKee, R. ; Loh, WK ; Houston, T. ; Garcia, R. ; Raval, J. ; Li, D. ; Hollingsworth, R. ; Gury, R. ; Eklund, R. ; Vaccani, J. ; Castellano, B. ; Piacibello, F. ; Ashburn, S. ; Tsao, A. ; Krishnan, A. ; Ondrusek, J. ; Anderson, T.
Abstract :
SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product´s lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor VT has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues
Keywords :
SRAM chips; thermal stability; 45 nm; 65 nm; SRAM arrays; SRAM memory cells; SRAM stability; VMIN drift; gate length scaling; negative bias temperature instability; screening methodology; system on chip devices; transistor threshold voltage; Failure analysis; Instruments; Negative bias temperature instability; Niobium compounds; Random access memory; Stability; System-on-a-chip; Testing; Threshold voltage; Titanium compounds;
