Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

Author

Dixit, A. ; Anil, K.G. ; Baravelli, E. ; Roussel, P. ; Mercha, A. ; Gustin, C. ; Bamal, M. ; Grossar, E. ; Rooyackers, R. ; Augendre, E. ; Jurczak, M. ; Biesemans, S. ; De Meyer, K.

Author_Institution

IMEC, Kapeldreef

fYear

2006

fDate

11-13 Dec. 2006

Firstpage

1

Lastpage

4

Abstract

Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin than resist-defined fins at VDD=1.2V. These SRAM test-cells achieve 130-nm planar-bulk comparable intra-bit-cell stochastic-mismatch and static noise margins

Keywords

CMOS integrated circuits; SRAM chips; circuit noise; 1.2 V; 130 nm; 32 nm; 55 nm; CMOS technology; FinFET SRAM; SRAM performance; intra-bit-cell stochastic-mismatch; line-edge-roughness; resist-defined fins; spacer-defined fins; static-noise-margin; stochastic mismatch; Area measurement; Circuit simulation; Electrical resistance measurement; FinFETs; Fluctuations; Random access memory; Resists; Resource description framework; Stochastic processes; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2006. IEDM '06. International

Conference_Location

San Francisco, CA

Print_ISBN

1-4244-0439-8

Electronic_ISBN

1-4244-0439-8

Type

conf

DOI

10.1109/IEDM.2006.346884

Filename

4154303