Title :
A high-throughput and size-efficient NoC buffer design method
Author :
Zhou, Wenbiao ; Liu, Zhenyu ; Zhang, Yanjun ; Wang, Siye ; Liu, Dake
Author_Institution :
ASIP Inst., Beijing Inst. of Technol., Beijing, China
Abstract :
This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffer´s size under NoC performance guarantee. Under the same buffer size, the experiments show that the method results in the 40% improvement of the throughput when compared the common input buffer design method.
Keywords :
buffer circuits; network routing; network synthesis; network-on-chip; performance evaluation; IP position mapping; application specific NoC; chip buffer; communication pair routing path; high-throughput NoC buffer design method; size-efficient buffer design method; Algorithm design and analysis; Calculus; Design methodology; IP networks; Multiplexing; Routing; Throughput; Buffer; Network Calculus; NoC; Throughput;
Conference_Titel :
Systems and Informatics (ICSAI), 2012 International Conference on
Conference_Location :
Yantai
Print_ISBN :
978-1-4673-0198-5
DOI :
10.1109/ICSAI.2012.6223160
