Title :
An overlapping min-sum LDPC decoder for IEEE 802.11n
Author :
Timakul, Sekson ; Tanyanon, I. ; Choomchuay, Somsak
Author_Institution :
Coll. of Data Storage Technol. & Applic., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand
Abstract :
This paper presents overlapping techniques designed for a compact hardware LDPC decoder with MS algorithm. The design is applicable to IEEE 802.11n standard. We elaborate how to reduce hardware and cycle time between row and column operation. The hardware utilization can be better enhanced and 16-40% cycle time reduction compared to a non-overlapping decoder can be achieved.
Keywords :
decoding; parity check codes; telecommunication standards; wireless LAN; IEEE 802.11n standard; cycle time reduction; hardware utilization; overlapping min-sum LDPC decoder; wireless LAN; Computer architecture; Field programmable gate arrays; Hardware; Lead; Logic gates;
Conference_Titel :
Intelligent Signal Processing and Communication Systems (ISPACS), 2010 International Symposium on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-7369-4
DOI :
10.1109/ISPACS.2010.5704671
