Low-power microarchitecture of zero-overhead nested loops in embedded processors

Instruction fetching usually consumes more than 50% of total power in embedded processors. In DSP applications, instructions to be fetched may come from loops mostly. This paper proposes a loop unit of low-power microarchitecture for nested looping and it is fully compatible with RISC pipeline architecture. A loop instruction set is designed to finish different kinds of loops. Branching, jumping and calling are also supported while looping. Performance and power analysis proves that great part of dynamic cycle counts and power consumption are saved. The loop unit integrated in embedded processors will improve the performance in execution of nested loops.