DocumentCode
2389979
Title
Strained Si and the future direction of CMOS
Author
Thompson, Scott E.
Author_Institution
Florida Univ., Gainesville, FL, USA
fYear
2005
fDate
20-24 July 2005
Firstpage
14
Lastpage
16
Abstract
Uniaxial process induced strain is being adopted in all 90, 65, and 45 nm high performance logic technologies. Uniaxial strain offers large performance improvement at low cost and minimally increased manufacturing complexity and is scalable to future technology nodes.
Keywords
CMOS logic circuits; elemental semiconductors; silicon; 45 nm; 65 nm; 90 nm; CMOS logic circuits; Si; logic technologies; strained silicon; uniaxial process induced strain; CMOS technology; Capacitive sensors; Costs; Dielectric substrates; High K dielectric materials; High-K gate dielectrics; Logic devices; Silicon; Tensile stress; Uniaxial strain;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN
0-7695-2403-6
Type
conf
DOI
10.1109/IWSOC.2005.99
Filename
1530908
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