DfM for SoC (design-for-manufacturability for system on a chip)

DfM (design-for-manufacturability) for efficient generation of mask data, optimization of manufacturing process, cost reduction, and best circuit performance of systems-on-chip are discussed. Beyond 100 nm technology node, layout pattern has to comply to many new requirements pertaining to database structure and complexity, suitability for image enhancement by the optical proximity correction, and mask data pattern density and distribution over the image field. A number of macro-, meso-, and microscopic effects such as reticle macroloading, planarization dishing, and pattern bridging or breaking would compromise fab yield, device performance, or both. This, given the already extremely high (and growing) process complexity, design cycle time and manufacturing cost, requires simulations to ensure that the first silicon out of the fab would yield. This work discusses the fundamentals of DfM in the area of layout best practices, mask data preparation, printability, and uniformization and the cost reduction.