A novel clock recovery scheme with improved jitter tolerance for PAM4 signaling

This paper introduces a novel clock recovery scheme for multilevel high speed serial data transmission. The system extracts the clock from a 10 Gb/s pulse amplitude modulated (PAM)-4 input signal. The output is non-return-to-zero (NRZ) data synchronized with the clock. Conventional methods recover the clock by over-sampling the received signal, which requires complicated circuit to implement. In contrast, the proposed method aligns the data with clock using three different transition levels of PAM4 signal. It is implemented with only a few additional blocks. We propose the scheme phase-loop-lock based CDR block with jitter reduction block in which the PAM4 signal is detected by each transition and converted to a binary signal. The proposed jitter reduction block consists of a differentiator, three comparators, monostable multivibrators and a decision block, while CDR part incorporates a phase and frequency detector, a loop filter and a voltage controlled oscillator (VCO). Due to the acquisition of each transition data, jitter is reduced and locking time for CDR is also reduced. We evaluate the system level architecture with PAM4 10 Gb/s signal and behavioral simulation.