Title :
4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes
Author :
Oh, Chang Woo ; Kim, Na Young ; Kim, Sung Hwan ; Choi, Yong Lack ; Hong, Sung In ; Bae, Hyun Jun ; Kim, Jin Bum ; Lee, Kong Soo ; Lee, Yong Seok ; Cho, Nam Myun ; Kim, Dong-Won ; Park, Donggun ; Ryu, Byung-Il
Author_Institution :
Device Res. Team, Samsung Electron. Co., Yongin
Abstract :
In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention
Keywords :
elemental semiconductors; nitrogen; semiconductor storage; silicon; 4 storage nodes; DSM; ONO layer thicknesses; double SONOS memories; multi level cell; multi level technology; single level cell; Flash memory; Interference; MOSFET circuits; Nonvolatile memory; Research and development; SONOS devices; Scalability;
Conference_Titel :
Electron Devices Meeting, 2006. IEDM '06. International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0438-X
Electronic_ISBN :
1-4244-0439-8
DOI :
10.1109/IEDM.2006.346947