Technologies for 3D wafer level heterogeneous integration

Author

Wolf, M.J. ; Ramm, P. ; Klumpp, A. ; Reichl, H.

Author_Institution

Fraunhofer IZM, Berlin

fYear

2008

fDate

9-11 April 2008

Firstpage

123

Lastpage

126

Abstract

3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.

Keywords

application specific integrated circuits; integrated circuit interconnections; system-in-package; wafer-scale integration; 3D wafer level heterogeneous integration; ASICs; high-density interconnects; passive silicon interposer; redistribution layers; sensors; stacked devices; system-in-package; through silicon vias; CMOS technology; Cost function; Fabrication; Isolation technology; Optimized production technology; Packaging; Silicon; System-on-a-chip; Through-silicon vias; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Test, Integration and Packaging of MEMS/MOEMS, 2008. MEMS/MOEMS 2008. Symposium on

Conference_Location

Nice

Print_ISBN

978-2-35500-006-5

Type

conf

DOI

10.1109/DTIP.2008.4752966

Filename

4752966