Parallel computing efficiency: climbing the learning curve

Parallel computing shows considerable potential to deliver cost-effective solutions to applications with high requirements in performance. However, current experience shows that performance often falls well below user expectations and below what would be considered cost-effective. Therefore, MPC hardware and software designers need to focus on the factors which affect parallel computing efficiency, if they are to narrow the gap between potential and delivered performance. Many analyses of parallel computing efficiency which have been reported are mainly too restrictive to provide helpful results. Thus, a different approach is required which would help parallel architecture and algorithm designers to climb the learning curve associated with parallel computing efficiency. In this paper, a performance analysis is introduced which makes a distinction between natural parallelism (which is inherent to an application) and applied parallelism (which can be observed when an application is implemented on an MPC). By highlighting parallel computing bottlenecks the analysis supports MPC hardware and software designers to identify causes for inefficiency. Furthermore helpful efficiency measures can be defined. The paper demonstrates the usefulness of the analysis and concludes that it could form the basis of a methodology which formalises the improvement of parallel computing efficiency