Author :
Han, J.P. ; Utomo, H. ; Teo, L.W. ; Rovedo, N. ; Luo, Zhengqian ; Krishnasamy, R. ; Stierstorfer, R. ; Chong, Y.F. ; Fang, Shao-Yun ; Ng, H. ; Holt, Jim ; Adam, T.N. ; Kempisty, J. ; Gutmann, A. ; Schepis, D. ; Mishra, Shivakant ; Zhuang, Hao ; Kim, Jongh
Abstract :
We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded
Keywords :
CMOS integrated circuits; Ge-Si alloys; internal stresses; 1 V; CMOS integration scheme; SiGe; channel strain; compressive stress liner; graded embedded; high performance CMOS devices; source/drain; stressor; CMOS process; CMOS technology; Capacitive sensors; Germanium silicon alloys; Performance gain; Semiconductor films; Silicides; Silicon germanium; Strain control; Stress;
