DocumentCode :
2390811
Title :
A hardware-accelerated framework with IP-blocks for application in MPEG-4
Author :
Amer, Ihab ; Rahman, Choudhury A. ; Mohamed, Tamer ; Sayed, Mohammed ; Badawy, Wael
Author_Institution :
Cagalry Univ., Calgary, Alta., Canada
fYear :
2005
fDate :
20-24 July 2005
Firstpage :
211
Lastpage :
214
Abstract :
In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.
Keywords :
field programmable gate arrays; video coding; IP-blocks; IP-quality assessment; MPEG-4; hardware blocks; hardware-accelerated framework; software reference model; Communication system control; Consumer electronics; Field programmable gate arrays; Hardware; MPEG 4 Standard; Prototypes; Robustness; Testing; Video coding; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN :
0-7695-2403-6
Type :
conf
DOI :
10.1109/IWSOC.2005.10
Filename :
1530944
Link To Document :
بازگشت