Efficient pattern-based emulation for IEEE 802.11a baseband

As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.