DocumentCode
2390963
Title
A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz
Author
Wang, Yanjie ; Khan, M. Zamin ; Iniewski, Kris
Author_Institution
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
fYear
2005
fDate
20-24 July 2005
Firstpage
247
Lastpage
251
Abstract
An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18μm CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author´s knowledge this is the lowest voltage supply CMOS LNA design reported to date.
Keywords
CMOS integrated circuits; microwave amplifiers; microwave integrated circuits; 0.18 micron; 0.65 V; 1.4 dB; 1.9 mW; 20 dB; 5 GHz; CMOS low-noise amplifier; CMOS technology; Spectre simulator; cascode topology; noise figure; power dissipation; Circuit noise; Inductance; Low-noise amplifiers; MOS devices; Noise figure; Noise generators; Noise level; Power supplies; Threshold voltage; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Print_ISBN
0-7695-2403-6
Type
conf
DOI
10.1109/IWSOC.2005.2
Filename
1530951
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